1. Field of the Invention
The present invention relates to a class-D power amplifier, and more particularly, to a class-D power amplifier that is able to prevent deterioration and breakage of a speaker caused by a direct current (DC) or an overcurrent that flows in the speaker in a case where a signal input terminal of the class-D power amplifier is suddenly short-circuited to a power-supply voltage or to a ground potential.
2. Description of Related Art
A speaker having a relatively low impedance of 4 Ω, 6 Ω, 8 Ω, or 16 Ω, for example, is connected with the last stage of a power amplifier that is used for a TV set, personal computer, AV receiver, car audio player and the like. Accordingly, even under usual use conditions, a relatively large load current flows in a power transistor and a speaker that is connected with the power transistor. Besides, it is not assured that a power amplifier always operates under proper conditions, and is often put in a state that deviates from a usual operation state because of a change in a situation. For example, a trouble can happen, in which a user handling a power amplifier inadvertently short-circuits a signal input terminal or a signal output terminal of the power amplifier to a power-supply voltage terminal or a ground terminal.
As one of power amplifiers, a class-D power amplifier of a bridge-connection load type is known. Generally, the bridge-connection load is also called a BTL (Bridge-Tied Load). Generally, it is known that as power amplifiers called “class-D,” there are some types of amplifiers. For example, a class-D power amplifier of a separately-excited oscillation PWM type is known. A class-D power amplifier of the separately-excited oscillation PWM type uses a triangular-wave signal as a carrier signal for modulating an analog signal. Accordingly, a triangular-wave signal generation circuit must be prepared. In a class-D power amplifier of the separately-excited oscillation PWM type, an analog signal is converted (called PWM: Pulse Width Modulation) into a pulse signal whose pulse width changes with time; a power transistor is turned on/off by the pulse signal; signals output from the power transistor are integrated by a low pass filter, so that a speaker is driven. Like the separately-excited oscillation PWM type, a well known class-D power amplifier of a self-excited oscillation PWM type includes an oscillator that is directly oscillated without requiring a triangular-wave generation circuit. Besides these PWM types, a class-D power amplifier of a Delta Sigma modulation type is also well known.
FIG. 7 is a block circuit diagram that simply shows a class-D power amplifier of the BTL type. A class-D power amplifier 100 is composed of a main circuit portion 110 and its external electronic components. The main circuit portion 110 includes: a signal input terminal 120; a preamplifier 130; a PWM modulation circuit 140; a first class-D driver 150; a second class-D driver 160; a first signal output terminal 152; and a second signal output terminal 162. The external electronic components include: inductors L1, L2; capacitors C1, C2, and C0; and a load RL. The load RL corresponds to a speaker.
When an analog signal Sin is input into the signal input terminal 120, the analog signal Sin is input into the preamplifier 130, that is, preamp 130. A gain adjustment circuit that has a gain adjustment function may be disposed in a back stage of the preamp 130. The analog signal output from the preamp 130 is input into the PWM modulation circuit 140. As the PWM modulation circuit 140, it is possible to employ the separately-excited oscillation PWM type that modulates an analog signal by using a triangular-wave signal as a carrier signal. From a first output terminal 141 of the PWM modulation circuit 140, a pulse-width-modulated signal P1 (hereinafter, called a PWM signal) that has a period T0 and a high-level time duration T1 is output. From a second output terminal 142 of the PWM modulation circuit 140, a PWM signal P2 that has a polarity opposite to the polarity of the PWM signal P1, that is, a complementary relationship with the PWM signal P1 is output. The duty ratio Pd of the PWM signals P1, P2 is expressed by Pd=T1/T0. The duty ratio Pd ranges from 0% to 100%. A power-supply voltage E1 is supplied to the PWM modulation circuit 140. The power-supply voltage E1 is 5 V, for example. Of course, instead of the separately-excited oscillation PWM type, a class-D power amplifier of the self-excited oscillation PWM type is also able to be used.
The PWM signals P1 and P2 respectively output from the first output terminal 141 and the second output terminal 142 are input into the first class-D driver 150 and the second class-D driver 160, respectively. A power-supply voltage E2 is supplied to the first and second class-D drivers 150 and 160. The power-supply voltage E2 ranges from 10 V to 30 V, and is generally set at a value larger than the power-supply voltage E1 that is supplied to the PWM modulation circuit 140.
A PWM signal P1a is output from a first signal output terminal 152 of the first class-D driver 150, while a PWM signal P2a is output from a second signal output terminal 162 of the second class-D driver 160. The PWM signal P1a and the PWM signal P2a are signals whose polarities are inverted from each other, and have a complementary relationship with each other. The PWM signal P1a has the same polarity as that of the PWM signal P1 but their amplitude values are different from each other. Generally, the amplitude values are substantially equal to the power-supply voltages E1, E2. This is true for the relationship between the PWM signal P2a and the PWM signal P2.
One end of the inductor L1 is connected with the first signal output terminal 152, while one end of each of the capacitors C1, C0, and the load RL is connected with the other end of the inductor L1. The inductor L1 and the capacitor C0 constitute a low pass filter; and the PWM signal P1a is demodulated as an analog output signal Sout1 by this low pass filter. The capacitor C1 has a function of a high pass filter. The load RL corresponds to a speaker and this speaker includes a voice coil.
One end of the inductor L2 is connected with the second signal output terminal 162, while one end of each of the capacitors C2, C0, and the load RL is connected with the other end of the inductor L2. The inductor L2 and the capacitor C0 constitute a low pass filter; and the PWM signal P2a is demodulated as an analog output signal Sout2 by this low pass filter. The capacitor C2 has a function of a high pass filter. The analog output signal Sout2 and the analog output signal Sout1 have a complementary relationship with each other.
FIG. 8 schematically shows a case where the signal input terminal 120 of the class-D power amplifier 100 is short-circuited to a power-supply voltage or to a ground potential. If the signal input terminal 120 is connected or made come into contact with a terminal 121 and a power-supply voltage Vcc is applied to the signal input terminal 120, the signal input terminal 120 is put into a state of a short-circuit to the power-supply voltage. If the signal input terminal 120 is connected or made come into contact with a terminal 122 and a ground potential is applied to the signal input terminal 120, the signal input terminal 120 is put into a state of a short-circuit to the ground potential.
In FIG. 8, if the signal input terminal 120 is electrically connected or made come into contact with the terminal 121 by an inadvertent operation, that is, short-circuited to a power-supply voltage, the power-supply voltage Vcc that is extremely deviated from a usual operation voltage is applied to the signal input terminal 120. Accordingly, circuit operations of the preamp 130 and the PWM modulation circuit 140 extremely deviate from a usual state, so that the PWM signal P1 that is kept at a duty ratio of 100% appears at the first output terminal 141 of the PWM modulation circuit 140. The PWM signal P1 that is kept at the duty ratio of 100% is put in a state in which the PWM signal P1 is kept at a high level that is substantially equal to the direct-current (DC) power-supply voltage E1 supplied to the PWM modulation circuit 140.
In the time the signal input terminal 120 is short-circuited to the ground potential, the PWM signal P2 appears at the second output terminal 142 of the PWM modulation circuit 140. Because the PWM signal P2 is a signal that is opposite to the PWM signal P1 in polarity, that is, a complementary signal, a low-level direct-current (DC) voltage that is kept at a duty ratio of 0% and substantially equal to the ground potential appears.
In the time the signal input terminal 120 is short-circuited to the power-supply voltage, the power-supply voltage E1 and the ground potential (GND) that respectively appear at the first output terminal 141 and the second output terminal 142 of the PWM modulation circuit 140 are transmitted to the first class-D driver 150 and the second class-D driver 160, respectively; and output from the first signal output terminal 152 and the second signal output terminal 162, respectively. Accordingly, in the time the signal input terminal 120 is short-circuited to the power-supply voltage, a potential difference between the first signal output terminal 152 and the second signal output terminal 162 becomes substantially equal to the power-supply voltage E2 supplied to the first class-D driver 150; and a direct-current (DC) component overcurrent ip flows from the first signal output terminal 152, through the load RL, that is, the speaker, and to the second signal output terminal 162. Because of the overcurrent ip, a trouble that the load RL (speaker) is deteriorated or broken can occur.
The above description is of a case where the signal input terminal 120 is short-circuited to a power-supply voltage. Next, a case where the signal input terminal 120 is short-circuited to a ground potential is briefly described. In FIG. 8, if the signal input terminal 120 is connected or made come into contact with a terminal 122 (GND), the signal input terminal 120 is put in a state of a short-circuit to a ground potential. If the signal input terminal 120 is short-circuited to a ground potential, a state that is electrically opposite to the state of a short-circuit to a power-supply voltage occurs. Specifically, a low-level voltage that is substantially equal to the ground potential (GND) appears at the first output terminal 141 of the PWM modulation circuit 140, while a high-level direct-current (DC) voltage that is substantially equal to the power-supply voltage E1 for the PWM modulation circuit 140 appears at the second output terminal 142.
These direct-current (DC) voltages that appear at the output sides of the PWM modulation circuit 140 are separately transmitted to the first class-D driver 150 and the second class-D driver 160 and separately output from the first signal output terminal 152 and the second signal output terminal 162. A low-level DC voltage appears at the first signal output terminal 152, while a direct-current (DC) voltage which is substantially equal to the power-supply voltage E2 supplied to the second class-D driver 160 appears at the second signal output terminal 162. Because the power-supply voltage E2 of the same magnitude is supplied to the first class-D driver 150 and the second class-D driver 160, the overcurrent ip that flows when the signal input terminal 120 is short-circuited to a ground potential flows in a direction opposite to the direction in the case of a short-circuit to a power-supply voltage, that is, from the second signal output terminal 162 to the first signal output terminal 152. In any case, also in the case where the signal input terminal 120 is short-circuited to the ground potential, the same overcurrent ip as that in the case of the short-circuit to the power-supply voltage flows. Accordingly, the trouble that the load RL (speaker) is deteriorated or broken can occur.
JP-A-2000-151297 (hereinafter, called a paten document 1) proposes a power amplification circuit that prevents breakage and thermal damage of a speaker caused by a short-circuited input. In other words, a power amplification circuit is proposed, which prevents deterioration and breakage of a speaker in a case where a signal input terminal is shirt-circuited to a ground potential. With reference to a paragraph [0018], it is suggested that if an input terminal of a BTL amplification circuit is short-circuited, an offset comes to constantly occur at an output of the power amplification circuit; and because of the short-circuit, the BTL amplification circuit is trapped into such a state as if a negative overcurrent is applied, so that an output current flows from a (−) output terminal to a (+) terminal via a load in the BTL amplifier.
JP-A-2008-17353 (hereinafter, called a patent document 2) proposes a class-D amplifier that prevents a DC output from being applied to a speaker. With reference to a paragraph [0005], it is pointed out that if a DC output is applied from the amplifier to the speaker and thus a state in which cone paper of the speaker is driven in a DC fashion continues, the speaker can be broken.
The patent document 2 discloses a class-D power amplifier that has a structure in which the class-D amplifier applies pulse width modulation to, that is, pulse-width-modulates an analog signal; generates and outputs first and second pulse signals whose duty ratios complementarily change depending on a signal level of the analog signal; wherein the class-D amplifier includes: a signal conversion portion which converts the first and second pulse signals into first and second signals that each complementarily have a predetermined level depending on the signal level of the analog signal; and a time count portion which detects that either of the first and second signals maintains the predetermined level for a predetermined time. Here, the “the predetermined level” means a low level or a high level that is maintained for the predetermined time. Besides, the “predetermined time” means a time, for example, 25 ms, that is counted by the time counting portion. The predetermined time, for example, 25 ms is equivalent to the period of a frequency of 40 Hz.
It is thought that the technical concept disclosed in the patent document 2 is characterized in that especially the signal conversion portion and the time count portion are included. It is said in advance that the technical concept of the time count portion is somewhat similar to the present invention described later.